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Posted: April 20th, 2022
VERILOG SIMPLE digit display
Question description
Design a finite state machine(FSM)that cycles through the last 4digits of your UTEP student ID in a loop. In your design there should be an input that changes thedirection of the cycle.Each number of the ID should be displayed on the seven-segment display while the current state of the FSM should be displayed on its corresponding LED.Non-valid states should keep all LEDs off.implement a clock as the synchronizing clock signal.For Example,a particular student has the ID 80-210543. The state diagram and outputs for his design are as followsFor Example, a particular student has ID 80210543. The state diagram and outputs for his de sign are as follows:0 @state05 @state14 @state23 @state3and then display backwardsPre-LabDraft the behavioral Verilog module for the FSM.Hint: You may use anif/ifelse/else statement or a“nested”case statement.Hint: search “Finite State Machines” inIntroduction to Verilog-P.M.Nyasulu
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